ADAPTEC MEMORY CONTROLLER / XOR ENGINE DRIVERS FOR WINDOWS 7


Download Now
Adaptec Memory Controller / XOR Engine Driver

Adaptec Memory Controller / XOR Engine Free Driver Download for Windows NT4, NT - . World's most popular driver. Adaptec Memory Controller / XOR Engine driver for Windows XP x86, or download DriverPack Solution software for automatic driver installation and update. Adaptec, Inc. (Milpitas, CA) A exclusive OR(XOR) accumulator engine of a memory controller, the XOR accumulator engine having an XOR.


ADAPTEC MEMORY CONTROLLER / XOR ENGINE DRIVERS WINDOWS

Type: Driver
Rating:
3.12
63 (3.12)
Downloads: 607
File Size: 17.8Mb
Supported systems: Windows 2008, Windows XP, Windows Vista, Windows 7/8/10
Price: Free* [*Free Registration Required]

Download Now
Adaptec Memory Controller / XOR Engine Driver

What is claimed is: An exclusive OR XOR accumulator engine for efficiently generating parity from a group of data blocks stored in memory of a data processing system, the XOR accumulator engine comprising: The XOR accumulator engine of claim 1 wherein the XOR logic circuit has a plurality of inputs coupled to a plurality of data sources and Adaptec Memory Controller / XOR Engine the multi-stage shift register has an input coupled to an output of the XOR logic circuit.

The XOR accumulator engine of claim 2 wherein one of the plurality of data sources is an output of Adaptec Memory Controller / XOR Engine multi-stage shift register coupled to one of the plurality of inputs of the XOR logic circuit, and wherein another of the plurality of data sources is the memory for providing the data blocks to another of the plurality of inputs of the XOR logic circuit.

ADAPTEC MEMORY CONTROLLER / XOR ENGINE DRIVER DOWNLOAD

The XOR accumulator engine of claim 1 wherein the register comprises a bypass circuit configured to create first and second stages of the multi-stage register, whereby to Adaptec Memory Controller / XOR Engine the register to accommodate the different sizes of the data blocks. The XOR accumulator engine of claim 4 wherein the bypass circuit comprises a tap multiplexer having a first input that couples to an output of the first stage, a second input that bypasses the first stage by intercepting data provided at an input of the multi-stage register and an output connected to an input of the second stage.

The XOR accumulator engine of claim 5 further comprising a control state machine for generating control signals used to control operations within the engine.

The XOR accumulator engine of claim 6 wherein a first control signal generated Adaptec Memory Controller / XOR Engine the state machine configures the tap multiplexer to select one of its first and second inputs to dynamically adjust the depth of the register to conform with a size of a data block loaded into the input of the multi-stage register.

The XOR accumulator engine of claim 7 wherein the multi-stage shift register comprises a plurality of cascaded storage elements interrupted by the tap multiplexer.

The XOR accumulator engine of claim 8 wherein each storage element comprises a set of flip-flops coupled to associated segment multiplexers. The XOR accumulator engine of claim 9 wherein the set of flip-flops are configured as a register segment. The XOR accumulator engine of claim 10 wherein the memory comprises a bi-directional memory interface having an input data path and an output data path coupled to a plurality of inputs of the XOR logic circuit.

The XOR accumulator engine of claim 11 wherein each of the input and Adaptec Memory Controller / XOR Engine data paths comprises a driver coupled to a latch.

ADAPTEC, INC. Adaptec Memory Controller / XOR Engine drivers for Windows XP x86

The XOR accumulator engine of claim 12 wherein the latch is a D-type flip-flop and the driver is a tri-state buffer circuit, and wherein the tri-state buffer circuit is enabled by a second control signal generated by the control state machine. The exclusive XOR accumulator engine of claim 14 wherein the multi-stage shift register comprises a plurality of cascaded storage elements.

ADAPTEC MEMORY CONTROLLER / XOR ENGINE DRIVER DOWNLOAD

The exclusive XOR accumulator engine of claim 15 wherein the bypass circuit is a tap multiplexer configured and arranged to interrupt the plurality of cascaded storage elements. The data to be protected are typically divided into Adaptec Memory Controller / XOR Engine or blocks of data that are further organized into data groups, each of which consists of a fixed number of data blocks.

For a data processing system having a plurality of data storage devices, e. In the context of a RAID implementation, parity protection denotes a type of checksum that allows regeneration of unreadable data in a block by evaluating a function of the data values stored in positionally corresponding data blocks Adaptec Memory Controller / XOR Engine are not in error. A memory controller of the data processing system generally performs such an evaluation, typically in connection with a Booleon exclusive OR XOR function.

The XOR function is applied bit-by-bit to positionally corresponding bits in each data block of a group and the result is stored in a positionally corresponding bit of a parity block. The parity block for each data grop is then stored on one of the disks containing the data group that the parity block protects. The system comprises a main memory coupled to a memory controller via a memory bus The main memory includes storage locations for holding data blocks B1-B4 of a data group transferred Adaptec Memory Controller / XOR Engine a plurality of disks not shown and the controller contains an XOR function for performing parity operations on the data blocks.

  • Publisher's Description

The results of the parity operations are then stored in a location in memory The memory controller typically calculates parity for the data blocks by way of a series of read and write operations over the memory bus For example, B1 is acquired from memory via a read access R1 over the busB2 is acquired via a read access R2 over the bus, parity is calculated from Adaptec Memory Controller / XOR Engine blocks and the partial result is stored in buffer via a write access Wp over the bus.

Likewise, data block B3 is acquired via a read bus access R3the parital parity result is retrieved via a read bus access Rpparity is calculated from these blocks and the partial result is stored via a write bus access Wp. Finally, B4 is acquired via a read bus access R4the parital parity result is retrieved via a read bus access Rp Adaptec Memory Controller / XOR Engine, parity is calculated from these blocks and the total parity result is stored via a write access Wt over the bus.

Table 1 summarizes these bus operations required to calculate parity for the data blocks B1-B4. Parity calculations requiring read and write bus accesses by the memory controller to main memory are time Adaptec Memory Controller / XOR Engine and, thus, inefficient. It is therefore desirable to reduce the number of memory bus accesses required for a memory controller to calculate parity for data blocks stored in a memory of a data processing system.

ADAPTEC MEMORY CONTROLLER / XOR ENGINE DRIVER DOWNLOAD

The present invention is generally Adaptec Memory Controller / XOR Engine to an arrangement for reducing those bus accesses and increasing the effciency of the parity calculation process. One known technique for generating parity blocks for use in a computer system is described in U. The first-in first-out FIFO based parity generator is coupled to a general purpose data bus and comprises a series of 1-bit parity circuits.

- Free download and software reviews - CNET

Each parity circuit includes a FIFO logic block comprising a ring buffer with read and write address counters. The ring buffer, in turn, comprises a series of 1-bit memory locations with a data signal input and a data signal output of the FIFO block. The read and write address counters are activated to deliver their contents Adaptec Memory Controller / XOR Engine the ring buffer in response to respective read and write control signals.

The FIFO-based parity generation technique is generally complex in terms of the control needed to manage read and write data operations to and from the ring buffer.

Drivers for manufacturers Adaptec to HardDisk Controllers

Adaptec Memory Controller / XOR Engine is, the address counters and other supporting logic circuits required to implement the FIFO advance a rather complex and expensive parity generator design. Accordingly, the present invention is directed to an inexpensive arrangement for increasing the efficiency of parity calculations in a data processing system. Broadly stated, the XOR engine comprises an XOR logic circuit coupled to a multi-stage shift register for accumulating parity calculations generated Adaptec Memory Controller / XOR Engine the logic circuit.

Accumulation of parity within the shift register continues until all of the data blocks within the group have been processed by the logic circuit; thereafter, the data blocks and their generated parity are stored on multiple disks of the data processing system.

In the illustrative embodiment of the present invention, the XOR accumulator engine is contained within a memory controller of the system and may be used to ensure the integrity of data stored on the multiple disks using known redundant array of independent disk RAID techniques.

Related Posts